Arbiter circuits can resolve (e.g., arbitrate) conflicts between two signals that can be activated essentially simultaneously. Arbiters can play an important role in devices such as dual port random access memories (RAMs) by arbitrating accesses to a same storage circuit via different ports. Arbiters generally have two “request” inputs and two “grant” outputs and resolve conflicts between two conflicting simultaneously received or asserted inputs.
A drawback to conventional asynchronous arbiters can be the presence of metastability conditions. A metastability condition can result from two simultaneously asserted inputs that result in both outputs being either high or at an approximately equal intermediate voltage level. A metastability condition can increase a resolution time by an indefinite amount. Consequently, timing cannot be guaranteed for cases where an arbiter circuit is susceptible to a metastable state.
To better understand various aspects of the embodiments, conventional arbiter circuits will now be described. A first conventional asynchronous arbiter is set forth in FIG. 5, and designated by the general reference character 500.
A first conventional arbiter circuit 500 can include a latch 502 and output logic 504. A drawback to such an arrangement can be that gates within latch 502 and output logic 504 can be trip point dependent. That is, assuming arbiter circuit 500 is formed from complementary metal-oxide-semiconductor (CMOS) devices, the point at which different values are latched within latch 502 can depend upon the threshold voltage of p-channel field effect transistors (PFETs) and n-channel FETs (NFETs) forming such circuits. At lower power supply voltages, the sum of PFET and NFET threshold voltages can exceed a minimum supply voltage. This can produce a region of uncertainty in operation, in which the latch 502 can enter an indeterminate (metastable) state. While gate sizes can be sized to skew a trip point, such approach may not be capable of ensuring operation over all anticipated operating conditions, including a range of power supply voltages, operating temperatures, as well as manufacturing process induced variations.
A second conventional solution 600 shown in FIG. 6 comprises a latch 602, a filter circuit 604, and a kicker circuit 606. A latch 602 can latch data values according to input signals MATCHR and MATCHL. A filter circuit 604 can help eliminate metastable states by including “always on” PFETs that can force arbiter outputs to predetermined levels absent a stable latching by latch 602. In addition, a kicker circuit 606 can force latch 602 into a given state after a predetermined delay in the event both inputs are driven high (potentially metastable inducing inputs).
A drawback to the arrangement of FIG. 6 can be that arbiter outputs BUSYBL and BUSYBR can be the same in a no address match state (both inputs low) and a metastable state (both inputs high, introducing metastability).